The SoÑAMoS project (Microelectronic Design Solutions and Architectures for Healthcare) focuses on the research and development of hardware-accelerated processing architectures optimised for Internet of Things (IoT) healthcare applications.
SoÑAMoS will also develop the associated tools required to efficiently assess the added value of these acceleration solutions, ensuring measurable benefits from their adoption.
Validation will be carried out incrementally, starting from COTS RISC-V devices as an initial reference, progressing through FPGA prototyping, and culminating in ASIC design and tape-out for fabrication.
Background
Computing requirements in IoT nodes have changed significantly as the distributed computing paradigm known as edge computing has gained relevance. Under this approach, processing shifts from high-performance cloud-based systems to being executed as close as possible to data sources, using higher-performance, energy-efficient embedded devices. This reduces latency and communication-related energy consumption between nodes and the cloud, while also improving aspects such as security and privacy. The project proposes the use of high-performance, energy-efficient embedded computing architectures deployed in IoT edge nodes.
General Project Objectives
Driven by the initial challenges identified in the executive summary, the following general objectives are defined for the project:
- OBJ1: Identify the processing architecture components of the SoÑAMoS RISC-V–based IoT platform, designed to operate under low-power constraints while meeting local processing capability requirements, incorporating innovative functionalities required in digital healthcare. Development and implementation on FPGA platforms, followed by ASIC design and fabrication.
- OBJ2: Research new hardware accelerators for IoT nodes in digital healthcare applications, including lightweight and post-quantum cryptographic algorithms, machine learning algorithms, and indoor positioning algorithms. Study the associated algorithmic operations and their mapping onto a RISC-V–based architecture with a tightly coupled accelerator, optimised for power consumption, silicon area and operational performance.
- OBJ3: Research new AI-based EDA tools for modelling RISC-V–based systems using virtual platform concepts. The objective is to support HW/SW co-design processes that reduce development and validation times for RISC-V–based IoT solutions.
- OBJ4: Research new packaging technologies to increase chip integration levels and improve the overall performance of the proposed solutions. Development and implementation of platforms meeting size reduction, reliability improvement and integration objectives.
- OBJ5: Conduct industrial experimentation to optimise the deployment and mapping of digital healthcare edge computing applications onto the RISC-V–based IoT SoC.
